1. Field of the Invention
The present invention relates to a measurement circuit, a measurement transistor, and measurement method capable of measuring a pinch-off voltage of a gate of a field effect transistor with a high precision. Further, the present invention relates to a method of manufacturing a junction field effect transistor using this measurement transistor to enable monitoring the pinch-off voltage of the junction field effect transistor formed on the same substrate and control of the gate threshold voltage after completion to a desired value.
2. Description of the Related Art
When forming a field effect transistor such as a metal-semiconductor field effect transistor (MESFET) and a junction field effect transistor (JFET) on a GaAs or other compound semiconductor substrate, for example, how precisely a gate threshold voltage Vth can be controlled is one of most important factors for determining the improvement of the manufacturing yield and the quality of the circuit characteristics.
For this reason, the method of monitoring the gate threshold voltage Vth in the middle of the wafer process and controlling the gate threshold voltage Vth after completion of the field effect transistor has been conventionally adopted as a procedure for enhancing the precision of control of the gate threshold voltage Vth.
When forming a junction field effect transistor on a GaAs substrate, first an n-type impurity diffusion region (channel forming impurity region) in which the channel is to be formed is formed on the surface side an a semi-insulating GaAs substrate, then a silicon nitride film or other film is formed on the entire surface. Next, a gate electrode forming portion is opened in this silicon nitride film to partially expose the channel forming impurity region, a p-type impurity is introduced via this open portion and the impurity is diffused in the channel forming impurity region to form the gate impurity region, which determines the gate threshold voltage Vth, while controlling the impurity concentration, depth, etc. thereof.
At the time of the diffusion when forming the gate impurity region, however, the substrate is exposed to a high temperature, therefore some ohmic electrodes having a low heat resistance such as AuGe/Ni cannot be provided in advance on the substrate and therefore the gate threshold voltage Vth must be controlled before the formation of the ohmic electrodes. For this reason, ohmic contacts with the channel forming impurity region cannot be obtained, therefore the gate threshold voltage Vth, which is defined by the characteristic of a drain current Id with respect to a voltage Vg applied between the source and drain under a predetermined drain bias (hereinafter, simply referred to as a "current-voltage characteristic"), cannot be measured. The situation is the same in the case of a MESFET as well if the gate threshold voltage Vth is measured before forming the ohmic electrodes.
Therefore, wide use has been made of the method of measurement of a pinch-off voltage Vp for measuring a change of capacitance of wide measurement patterns formed together with the gate impurity region in place of the gate threshold voltage Vth defined by the current-voltage characteristic.
In the process of manufacturing of a MESFET, generally use is made of the method using mercury probes, but here an explanation will be made of the method of measurement of the pinch-off voltage Vp of the related art using the change of capacitance of the above wide measurement pattern taking as an example the process of manufacture of a junction field effect transistor.
FIG. 10A is a plan view of the pattern after a gate diffusion step for measuring the pinch-off voltage in a process of manufacturing a junction field effect transistor of the related art. Also, FIGS. 10B to 10E are sectional views of manufacturing steps of the junction field effect transistor of the related art. The right side of each view indicates a pattern for measurement of a pinch-off voltage (a measurement use pattern) in a test element group (TEG), and the left side indicates a junction field effect transistor.
First, as shown in FIG. 10B, n-type channel forming impurity regions 101 and 101a are formed on the surface side in a semi-insulating GaAs substrate 100. In the subsequent FIG. 10C, a gate impurity region 102 of the junction field effect transistor and a source measurement impurity region 103a and drain measurement impurity region 103b of the measurement use pattern are formed. In this method of formation, first a silicon nitride film or other film is formed, opening portions 104a, 104b, and 104c are formed in this, then a diffusion mask 104 is formed. A p-type impurity, for example, zinc (Zn) is diffused from the top of this diffusion mask 104 to the substrate so as thereby to simultaneously form the gate impurity region 102, the source measurement impurity region 103a, and the drain measurement impurity region 103b. As the diffusion method, a vapor phase diffusion method using for example Zn (C.sub.2 H.sub.5).sub.2 as the diffusion source is used.
As shown in FIG. 10D, first, a gate electrode 105 made of a stacked metal film of for example Ti/Pt/Au is formed in a manner buried in the opening portion 104a of the silicon nitride film on the gate impurity region 102. Further, ohmic electrodes 106 and 106 are formed at predetermined distances from the gate electrode 105. The formation of the ohmic electrodes 106 is achieved by making an opening in the silicon nitride film, forming a stacked metal film of AuGe/Ni on the surface of the exposed substrate, and heating this to make an alloy with the GaAs. Thereafter, a metal interconnection layer 107 for lowering the resistance is formed on the ohmic electrode 106 to thereby complete the fundamental structure of the junction field effect transistor.
In the process of manufacturing of a junction field effect transistor, the gate threshold voltage Vth of the junction field effect transistor is controlled in the diffusion step to the gate impurity region of FIG. 10C. This control is carried out by repetition of additional diffusion to the gate impurity region 102 and measurement of the pinch-off voltage Vp of the measurement use pattern until the pinch-off voltage Vp of the channel, which is correlated with the gate threshold voltage Vth, reaches the desired value.
The pattern for measurement of the pinch-off voltage Vp shown at the right side of FIG. 10A is used for this measurement.
In FIG. 10A, J1 is a first PN junction diode formed between the channel formation impurity region 101a and the source measurement impurity region 103a, while J2 is a second PN junction diode formed between the channel forming impurity region 101a and the drain measurement impurity region 103b. Two PN junction diodes J1 and J2 have a surface area sufficient for placement of the probes (for example the length of one side is about 100 to 150 .mu.m) and have a junction capacitance large enough for measurement.
On the other hand, the dimensions of the gate impurity region 102 of the junction field effect transistor drawn at the left side of FIG. 10A are for example a length Lg of the channel direction thereof of 0.5 .mu.m and a width Wg of the channel width direction of about 10 .mu.m.
Accordingly, the junction areas of the PN junction diodes J1 and J2 are much larger than the junction area of the gate impurity region 102 of the junction field effect transistor.
In a pattern for measurement of the pinch-off voltage Vp configured in this way, probes are brought into sufficient contact with the source measurement impurity region 103a and the drain measurement impurity region 103b and a capacitance-voltage meter is connected between these probes. At this time, the probes are placed so that the source measurement impurity region 103a is connected to the positive pole side of the capacitance-voltage meter, while the drain measurement impurity region 103b is connected to the negative pole side.
When applying a voltage between these two probes and measuring the capacitance-voltage characteristic, the capacitance-voltage curve of FIG. 11 is obtained. In the capacitance-voltage curve of FIG. 11, an extrapolated value Vpo of the voltage V applied when the value of the detected capacitance C sharply changes becomes a voltage when the channel forming impurity region 101 is pinched off, that is, an approximation of the pinch-off voltage Vp, due to the spread of the carrier depletion region of the PN junction diode J2 on the drain side.
The principle of measurement of this pinch-off voltage Vp will be explained using FIG. 12. In FIG. 12, C11 and C21 represent the junction capacitances of the bottom surfaces of the PN junctions J1 and J2, while C12 and C22 represent the junction capacitances of the side surfaces of the PN junctions J1 and J2. Further, R1 and R2 are resistances of the channel forming impurity regions 110a just under the PN junctions J1 and J2, while V is the voltage applied via the probes.
At the time of the measurement, most of the voltage V is applied on the PN junction J2 at the negative pole side, and the carrier depletion region D2 of the PN junction J2 spreads. When the voltage V is lower than the pinch-off voltage Vpo of the channel (A point of FIG. 11), the equivalent circuit shown in FIG. 12A is obtained. The detected capacitance C of the capacitance-voltage meter is represented by the following equation: EQU C=(C11+C12)//(C21+C22).apprxeq.C11//C22 (1)
Here, "//" is an operation code indicating that the two capacitances Cx and Cy are connected in series and is represented as Cx//Cy=Cx.multidot.Cy/(Cx+Cy). As described above, C11 and C21 are large capacitances of for example about 10 pF, therefore the above approximation equation (1) stands. Also, the detected capacitance C becomes a value of substantially the same order as the junction capacitances C11 and C21.
When the applied voltage V exceeds the pinch-off voltage Vpo of the channel (B point of FIG. 11), the equivalent circuit shown in FIG. 12B is obtained and the channel is pinched off under the junction capacitance J2 the negative pole side. When the channel is pinched off, the resistor R2 at the negative pole side of the channel forming impurity region 110a becomes open and is replaced by a very small substrate capacitance Csub in the equivalent circuit. The detected capacitance C of the capacitance-voltage meter at this time is shown by the following equation: EQU C=(C11+C12)//{(C21//Csub)+C22}.apprxeq.C11//(Csub+C22).apprxeq.Csub+C22(2)
Here, Csub is much smaller than C21, i.e., about for example 300 fF. Further, C22 is smaller than C21 by several orders due to the difference of junction areas. For this reason, the serial capacitance C21//Csub of the junction capacitance C21 and the substrate capacitance Csub is suppressed by the extremely small substrate capacitance Csub and becomes a value near Csub, while similarly C11//(Csub+C22) becomes a value near the smaller (Csub+C22). The approximation equation (2) indicate this by an equation.
As apparent from a comparison of the above two approximation equations (1) and (2), the detected capacitance C of the capacitance-voltage meter sharply changes before and after the pinch-off. Accordingly, the sharp change of the capacitance value of FIG. 11 is brought out by the pinch-off of the channel. By obtaining a grasp of this change of the capacitance, it therefore becomes possible to obtain a monitor value Vpo of the pinch-off voltage Vp. This principle of measurement is the same as in the measurement of the capacitance-voltage characteristic using mercury probes used often as the method of control of the gate threshold voltage Vth of a MESFET.
However, the pinch-off voltage Vpo measured by the above method does not match the gate threshold voltage Vth of the junction field effect transistor formed on the same substrate. Further, an unpredictable fluctuation is sometimes observed in the difference of the two (hereinafter referred to as ".DELTA.Vth").
If .DELTA.Vth is not constant, it cannot be determined how to set a target for the pinch-off voltage Vpo obtained by measuring the capacitance-voltage characteristic of the measurement pattern of FIG. 10 so as to obtain the desired gate threshold voltage Vth in the junction field effect transistor. Namely, in the method of measurement of the pinch-off voltage of the related art, there was the problem that even if the pinch-off voltage Vp was controlled taking it into account that .DELTA.Vth would become a certain value, the gate threshold voltage Vth of the actually formed junction field effect transistor would sometimes deviate from the expected value and high precision control thereof was difficult.
To solve this problem, the method of placing probes at gate pads led out from gates of the junction field effect transistor and directly measuring the gate threshold voltage Vth can be considered. However, the gate capacitance of a junction field effect transistor is for example only about several fF, therefore it is very difficult to directly and correctly measure it.
Further, there also exists the method of increasing the gate width Wg and number of gate fingers so as to increase the capacitance measured, but in this method, the amount of reduction of the capacitance at the pinch-off ends up being reduced and no sharp change in capacitance appears, therefore high precision detection of the pinch-off point is difficult. This is because the ratio of junction capacitances (ratio of junction areas) of the bottom surface with respect to the side surface of the gate impurity region 102 becomes small since the gate length Lg is made narrower. This ratio of capacitances does not change even if the gate width Wg is greatly increased. Of course, there is a more conspicuous tendency for reduction of the dynamic range of this change of capacitance as the gate length Lg is made shorter. The method of increasing the measured capacitance therefore cannot be adopted at all as the method of measurement of the gate threshold voltage Vth of a junction field effect transistor where gates are being made increasingly smaller.
In this way, the method of control of the gate threshold voltage Vth of a field effect transistor of the related art was not sufficient in precision. Particularly, in junction field effect transistors having PN junction gates or MESFETS having Schottky junction gates or other devices, it is important how precisely the gate threshold voltage Vth is controlled. Further, the number of factors causing variations in the gate threshold voltage Vth is increased in the process along with the increasing miniaturization of the gates. Accordingly, a higher precision method of control of the gate threshold voltage Vth has been demanded.